JPS60180127A - 樹脂封止型半導体装置の製造方法 - Google Patents
樹脂封止型半導体装置の製造方法Info
- Publication number
- JPS60180127A JPS60180127A JP59036679A JP3667984A JPS60180127A JP S60180127 A JPS60180127 A JP S60180127A JP 59036679 A JP59036679 A JP 59036679A JP 3667984 A JP3667984 A JP 3667984A JP S60180127 A JPS60180127 A JP S60180127A
- Authority
- JP
- Japan
- Prior art keywords
- substrate support
- lead
- resin
- external
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000011347 resin Substances 0.000 title claims abstract description 15
- 229920005989 resin Polymers 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000008188 pellet Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 6
- 238000007789 sealing Methods 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910017937 Ag-Ni Inorganic materials 0.000 description 1
- 229910017984 Ag—Ni Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59036679A JPS60180127A (ja) | 1984-02-27 | 1984-02-27 | 樹脂封止型半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59036679A JPS60180127A (ja) | 1984-02-27 | 1984-02-27 | 樹脂封止型半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60180127A true JPS60180127A (ja) | 1985-09-13 |
| JPH0234457B2 JPH0234457B2 (en]) | 1990-08-03 |
Family
ID=12476536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59036679A Granted JPS60180127A (ja) | 1984-02-27 | 1984-02-27 | 樹脂封止型半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60180127A (en]) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63303580A (ja) * | 1987-06-04 | 1988-12-12 | Olympus Optical Co Ltd | 固体撮像装置 |
| JPH02114542A (ja) * | 1988-10-24 | 1990-04-26 | Rohm Co Ltd | 半導体装置におけるモールド部の成形装置 |
| US5018003A (en) * | 1988-10-20 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Lead frame and semiconductor device |
| JP2002252319A (ja) * | 2001-02-23 | 2002-09-06 | Nippon Inter Electronics Corp | 半導体装置及びその製造方法、並びにリードフレーム |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53118478A (en) * | 1977-03-25 | 1978-10-16 | Hitachi Ltd | Resin molded products, their manufacture, and molding tool for it |
-
1984
- 1984-02-27 JP JP59036679A patent/JPS60180127A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53118478A (en) * | 1977-03-25 | 1978-10-16 | Hitachi Ltd | Resin molded products, their manufacture, and molding tool for it |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63303580A (ja) * | 1987-06-04 | 1988-12-12 | Olympus Optical Co Ltd | 固体撮像装置 |
| US5018003A (en) * | 1988-10-20 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Lead frame and semiconductor device |
| US5096853A (en) * | 1988-10-20 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing a resin encapsulated semiconductor device |
| JPH02114542A (ja) * | 1988-10-24 | 1990-04-26 | Rohm Co Ltd | 半導体装置におけるモールド部の成形装置 |
| JP2002252319A (ja) * | 2001-02-23 | 2002-09-06 | Nippon Inter Electronics Corp | 半導体装置及びその製造方法、並びにリードフレーム |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0234457B2 (en]) | 1990-08-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |